1. Field of the Invention
The present invention relates to a solid-state imaging device, a camera system, and a signal reading method.
Priority is claimed on Japanese Patent Application No. 2009-095916, filed Apr. 10, 2009, the content of which is incorporated herein by reference.
2. Description of Related Art
Generally, as solid-state imaging devices, MOS-type solid-state imaging devices that use pixels having an amplified reading function are known. FIG. 11 shows the pixel configuration of the MOS-type solid-state imaging device. A pixel 100 shown in FIG. 11 includes a photodiode 101, a transfer transistor 102, an electric charge maintaining unit (FD: floating diffusion) 103, a floating diffusion reset transistor 104, an amplifier transistor 105, a selection transistor 106, and a photodiode reset transistor 107. In addition, a pixel power source line 110, a floating diffusion reset line 111, a transmission line 112, a selection line 113, a vertical signal line 114, and a photodiode reset line 115 are shared by a plurality of pixels.
The photodiode 101 is a photoelectric conversion device in which the amount of accumulated electric charges changes in accordance with incident light. The transfer transistor 102 is a transistor that is used for transferring signal electric charges generated in the photodiode 101 to the electric charge maintaining unit 103. The electric charge maintaining unit 103 has an electric charge maintaining function for maintaining the electric charges transferred from the photodiode 101. The floating diffusion reset transistor 104 is a transistor that is used for resetting the electric charge maintaining unit 103. The amplifier transistor 105 is a transistor used for amplifying and reading out the voltage level of the electric charge maintaining unit 103. The selection transistor 106 is a transistor that is used for transferring the output of the amplifier transistor 105 to the vertical signal line 114 by selecting a pixel. The photodiode reset transistor 107 is a transistor that is used for resetting the photodiode 101. Here, the above-described components other than the photodiode 101 are light-shielded.
The pixel power source line 110 is a wiring used for applying a power source voltage VDD. The pixel power source line 110 is electrically connected to the drain side of the floating diffusion reset transistor 104, the drain side of the amplifier transistor 105, and the drain side of the photodiode reset transistor 107. The floating diffusion reset line 111 is a wiring for applying a floating diffusion reset pulse φRMi that is used for resetting the electric charge maintaining units 103 of one row. The floating diffusion reset line 111 is connected to the gates of the floating diffusion reset transistors 104 of one row.
The transmission line 112 is a wiring to which a row transmission pulse φTRi used for transferring signal electric charges of pixels of one row to the electric charge maintaining units 103 of the pixels is applied. The transmission line 112 is electrically connected to the gates of the transfer transistors 102 of the pixels of one row. The selection line 113 is a wiring to which a row selection pulse φSEi used for selecting pixels of one row is applied. The selection line 113 is electrically connected to the gates of the selection transistors 106 of pixels of one row. The photodiode reset line 115 is a wiring to which a row photodiode reset pulse φRPDi used for resetting the photodiodes 101 of one row is applied. The photodiode reset line 115 is connected to the gates of the photodiode reset transistors 107 of one row. As described above, by employing the pixel configuration using five transistors, a photoelectric conversion function, a photodiode resetting function, an electric charge maintaining unit resetting function, an amplified reading function, a temporary memory function, and a selection function are implemented.
The MOS-type solid-state imaging device has a pixel array in which the pixels having the above-described configuration are arranged in a two-dimensional pattern of m rows×n columns. FIG. 10 shows the configuration of the solid-state imaging device. The solid-state imaging device shown in FIG. 10 is configured by a pixel unit 200, a vertical scanning circuit 300, a horizontal signal reading circuit 400, a current source 150, and various wirings.
The pixel unit 200 represents a structure in which the pixels 100 shown in FIG. 11 are arranged in a two-dimensional 3×3 pattern. The vertical scanning circuit 300 performs driving control of pixels in units of one row. In order to perform the driving control, the vertical scanning circuit 300 is configured by unit circuits 301-i (i=1 to 3) that are disposed in correspondence with the number of the rows. The unit circuit 301-i of each row is configured by control units 302-i, 303-i, 304-i, and 305-i. 
The control unit 302-i controls the floating diffusion reset pulse φRMi independently for each row. The control unit 303-i controls the row transmission pulse φTRi independently for each row. The control unit 304-i controls the photodiode reset pulse φRPDi independently for each row. In addition, the control unit 305-i controls the row selection pulse φSEi independently for each row. The signals of pixels of the row selectively controlled in accordance with pulses are output to the vertical signal lines 114 that are disposed for each row.
The horizontal reading circuit 400 outputs the signals of pixels of one row that are output to the vertical signal lines 114 from the output terminal 410 in the alignment sequence of the horizontal direction in a time series. The current source 150 is connected to the vertical signal line 114 so as to provide a bias current. The floating diffusion reset line 111 is a wiring to which the floating diffusion reset pulse φRMi is applied. The transmission line 112 is a wiring to which the row transmission pulse φTRi is applied. In addition, the selection line 113 is a wiring to which the row selection pulse φSEi is applied. The photodiode reset line 115 is a wiring to which the photodiode reset pulse φRPDi is applied. Here, the pixel power source line 110 that supplies the pixel power source VDD is not shown in the figure.
A technique for reading out signals of all the pixels by reading out the signals of pixels of each row by sequentially selecting the first row to the m-th row under the above-described configuration is referred to as an ordinary XY address reading method. However, in the ordinary XY address reading method, the time at which the signal is accumulated is different for each row of the pixel array. Accordingly, the time for reading out a signal in the first row in which the signal is read out first and in the m-th row in which the signal is read out finally is different by a maximum of one frame. As a result, there is a problem in that an image is distorted in a case where an object moving at a high speed is photographed.
As a technique for solving the above-described problem, a global shutter reading method (for example, see Japanese Unexamined Patent Application, First Publications Nos. 2005-65184 and 2006-262070) is used. Hereinafter, the operation of the global shutter reading method will be described with reference to FIG. 12. First, the photodiode reset pulses φRPD1 to φRPDm of all the rows are set to a “Hi” level from the vertical scanning circuit 300. Accordingly, the photodiodes 101 of all the rows are in the reset state.
Subsequently, the floating diffusion reset pulse φRM1 of the first row is set to the “Hi” level, and thereby the electric charge maintaining units 103 of the first row are reset. Thereafter, the floating diffusion reset pulse φRM1 of the first row is set to a “Lo” level, and thereby the row transmission pulse φSE1 of the first row is set to the “Hi” level. Accordingly, a reset signal that is formed by a fixed pattern noise such as a reset noise and a variation of the threshold voltage of the source follower amplifier transistor is output through the vertical signal line 114 and the horizontal signal reading circuit 400. The output reset signal is stored in an external signal memory unit not shown in the figure. The above-described driving operation is performed sequentially for each row, and reset signals of all the rows are stored in the signal memory unit. Thereafter, the photodiode reset pulses φRPD1 to φRPDm are simultaneously set to the “Lo” level. Accordingly, accumulation of electric charges in pixels of all the rows is started at the same time.
After a predetermined period elapses, the floating diffusion reset pulses φRM1 to φRMm of all the rows are simultaneously set to the “Hi” level. Accordingly, the accumulation of electric charges in the pixels of all the rows is completed at the same time, and unnecessary electric charges of the signal electric charge maintaining unit 103 are discharged. Thereafter, the row transmission pulses φTR1 to φTRm of all the rows are set to the “Hi” level, and accordingly, the signal components (captured image signals) generated by the accumulation (exposure) for all the rows are transmitted altogether to the signal electric charge maintaining units 103.
Thereafter, the row selection pulses φSE1 to φSEm are set to the “Hi” level sequentially from the first row, and thereby captured image signals are output through the vertical signal line 114 and the horizontal signal reading circuit 400. By taking a difference between the output captured image signal component and the reset signal component stored in advance, only the captured image signal portion can be extracted by eliminating the reset noise and the fixed pattern noise. Therefore, an image having a high SN can be acquired.
By performing the above-described operation, the timings for the start and the end of accumulation of electric charges in the pixels of all the rows are the same. Accordingly, even in a case where a subject moves at a high speed, the subject is not captured in a distorted shape and a flicker of a fluorescent lamp does not appear in the image. Therefore, an image having a high image quality can be photographed.
In the related art, however, a driving method of sequential driving time (for example, an action mode) is not considered. FIG. 13 is a view showing a frame format of a concept in case that the driving shown in FIG. 12 is applied to sequential driving. In FIG. 13, the operation for one frame is configured by a sequential read-out operation 601 of reset signals, a batch accumulation starting operation 602, a batch transmission operation 603, and a sequential read-out operation 604 of captured image signals. A standby period 605 exists between a sequential read-out operation 604 of captured image signals and a sequential read-out operation 601 of reset signals of the next frame. In sequential driving, since the above-described standby period 605 arises, a speed-up of continuous shooting is hindered.